SE-CSA based IN-D SG disturb free Volatile static memory using Fin-FET with Steep subthreshold sleep

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Published: Apr 30, 2025
Keywords:
Short gate Single Ended Current Sense Amplifier Static noise margin Input dependent double gate Delay Write and Read Power Leakage power

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Shyam.K*
Research Scholar, Department of ECE, Sathyabama Institute of Science and Technology, (Deemed to be University) Chennai –600119, Tamil Nadu, India.
V.Vijay Kumar
Associate Professor, Department of ECE, Sathyabama Institute of Science and Technology, (Deemed to be University) Chennai –600119, Tamil Nadu, India.

Abstract

FinFET, or Fin Field-Effect Transistor, is a type of transistor used in modern semiconductor devices to overcome the limitations of traditional planar transistors as scaling continues in the nanometer range. Characterized by a three-dimensional structure, the FinFET features a "fin" shape that extends vertically from the substrate, allowing for better electrostatic control over the channel and reduced leakage currents. This design enhances performance, improves switching speed, and allows for lower power consumption compared to conventional transistors. This paper presents a novel approach to static random-access memory (SRAM) design utilizing Shorted Gate Fin-FET (SG-Fin-FET) and Independent Gate Fin-FET (IG-Fin-FET) technologies at a 7-nm process node. The proposed 8T SRAM cell architecture, which excludes read and write transistors, effectively addresses the limitations of traditional SRAM configurations by decoupling the read and write operations. This decoupling enhances the Static Noise Margin (SNM), which is measured to be approximately 0.15 V, and significantly improves the Power Delay Product (PDP), achieving a reduction of 40% compared to conventional SRAM designs. The Input Dependent (INDEP) technique employed reduces leakage power dissipation by nearly 50%, thereby enhancing overall energy efficiency. Simulation results indicate a notable improvement in write capability, with a write margin of 0.2 V. The segmented array design allows for larger memory arrays without sacrificing performance, supporting up to 1 MB of data storage while maintaining an area efficiency of 0.35 μm² per cell. The proposed methodology demonstrates superior flexibility in optimizing read and write functionalities, resulting in improved performance metrics suitable for high-density memory applications. The results affirm the viability of using SG-Fin-FET and IG-Fin-FET technologies for next-generation SRAM cells, offering significant advancements in both power efficiency and operational performance.

Article Details

Issue
Vol. 167 No. A2 (S) (2025): Technologies and Their Effects on Real-Time Social Development
Section
Articles

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